Typically, a computer system includes a number of integrated circuit chips that communicate with one another to perform system applications. Often, the computer system includes a controller, such as a micro-processor, and one or more memory chips, such as random access memory (RAM) chips. The RAM chips can be any suitable type of RAM, such as dynamic RAM (DRAM), double data rate synchronous DRAM (DDR-SDRAM), low power SDRAM (LP-SDRAM), and/or pseudo static RAM (PSRAM). The controller and memory communicate with one another to perform system applications.
Some computer systems operate in mobile applications and have limited space and power resources. In mobile applications, such as cellular telephones and personal digital assistants (PDAs), memory cell density and power consumption are issues for current and future generations. Low power mobile RAM is a LP-SDRAM that has been developed for mobile applications. CellularRAM is a high performance and low power memory designed to meet memory density and bandwidth demands of current and future generations. CellularRAM is a PSRAM that offers static RAM (SRAM) pin and function compatibility, external refresh-free operation, and a low power design. CellularRAM devices are drop-in replacements for most asynchronous low power SRAMs used in mobile applications, such as cellular telephones. A PSRAM includes DRAM that provides significant advantages in density and speed over traditional SRAM.
Typically, a memory chip includes periphery circuitry and an array of memory cells. The periphery circuitry includes circuits that interface between the array of memory cells and the system controller. Often, the array of memory cells is divided into a number of banks of memory cells, such as two banks, four banks, eight banks or more banks.
The design of a memory chip in a selected process and interface technology takes many months of development. Some of this development can be reused to create memory devices in the same technology, but with different memory sizes. To create a memory chip having a different memory size, the periphery circuitry and the array of memory cells are changed schematically to adjust for the different memory size. Also, a new floor plan and significant layout effort is often needed to reshape an existing layout and optimize the memory device to a competitive integrated circuit chip size. Changing the periphery circuitry and the array of memory cells and laying out the memory chip via a new floor plan can be time consuming processes that increase the time to market and the cost of the integrated circuit chip.
For these and other reasons there is a need for the present invention.